<processor> An extension to the Advanced RISC Machine
architecture, announced on 06 March 1995 by Advanced RISC
Machines Ltd. By identifying the critical subset of the ARM
instruction set and encoding it into 16 bits, ARM has
succeeded in reducing typical program size by 30-40% from
ARM's already excellent code density. Since this Thumb
instruction set uses less memory for program storage, cost is
further reduced.
All Thumb-aware processor cores combine the capability to
execute both the 32-bit ARM and the 16-bit Thumb instruction
sets. Careful design of the Thumb instructions allow them to
be decompressed into full ARM instructions transparently
during normal instruction decoding without any performance
penalty. This differs from other 32-bit processors, like the
Intel 486SX, with a 16-bit data bus, which require two
16-bit memory accesses to execute every 32-bit instruction and
so halve performance.
The patented Thumb decompressor has been carefully designed
with only a small amount of circuitry additional to the
existing instruction decoder, so chip size and thus cost do
not significantly increase. Designers can easily interleave
fast ARM instructions (for performance critical parts of a
program) with compact Thumb code to save memory.
(1995-03-14)
Nearby terms:
three-tier « throughput « thud « Thumb » thumb » thumbnail » Thunderbird
